The present invention relates to a comparator that compares two input voltages with each other and that outputs a signal corresponding to a result of comparison, and more particularly to a comparator made up of a field effect transistor.
As is well known, a comparator is a circuit that compares two voltages with each other and that outputs a signal showing a result of comparison. Of circuits that compare two voltages by means of a comparator of this type and that process a signal showing a result of comparison, some are designed to process the signal showing a result of comparison at a source voltage that is lower than two voltages to be compared for reasons of; for example, an attempt to save power consumed by an entire circuit. FIGS. 3A and 3B show such circuit configurations, respectively.
In a circuit shown in FIG. 3A, voltages A and B, which are objects of comparison, are delivered to source follower circuits 40a and 40b, respectively. The source follower circuit 40a is made up of a voltage dividing circuit including an N-channel field effect transistor 41a whose drain is connected to the power source and whose gate is provided with the voltage A and resistors 42a and 43a interposed between a source of the N-channel field effect transistor 41a and an earth. The source follower circuit 40b is also made up of an N-channel field effect transistor 41b and resistors 42b and 43b, which exhibit a similar relationship of connection. A source voltage PVDD applied to the source follower circuits 40a and 40b must be a voltage that surpasses at least the upper limits of the voltages A and B serving as objects of comparison. A comparator 50 and subsequent circuits, which are at a stage subsequent to the source follower circuits 40a and 40b, are provided with a source voltage AVDD that is lower than the source voltage PVDD supplied to the source follower circuits 40a and 40b. In this configuration, the source follower circuit 40a (40b) applies the input voltage A (B) to the voltage dividing circuit made up of the resistors 42a and 43a (the resistors 42b and 43b), to thus divide the voltage, and voltages va and vb, into which the input voltage A (B) is compressed, are applied to the comparator 50. The comparator 50 compares the thus-compressed voltages va and vb with each other. As mentioned above, the circuit configuration utilizing the source follower circuit is described in; for instance, JP-A-2007-142709.
In the circuit shown in FIG. 3B, a comparator 60 disposed at a preceding stage is provided with the source voltage PVDD that surpasses at least the upper limits of the voltages A and B serving as objects of comparison. A circuit subsequent to a level shift circuit 70 is supplied with the source voltage AVDD that is lower than the source voltage PVDD supplied to the comparator 60. Both source voltages are supplied to the level shift circuit 70. In accordance with a result of comparison between the voltages A and B, the comparator 60 outputs a signal Vx of 0 volt or having a level in the vicinity of the source voltage supplied to the comparator 60. The level shift circuit 70 poses a limitation on the level of the signal Vx output from the comparator 60; converts the signal into a signal Vout whose upper limit is equal to the source voltage AVDD applied to the circuit subsequent to the level shift circuit 70; and supplies the thus-converted signal to the subsequent circuit.
However, in the circuit shown in FIG. 3A, when the source voltage supplied to the source follower circuits 40a and 40b decrease, a potential difference va-vb of each of the output signals is compressed. When the potential difference va-vb is compressed as mentioned above, operation of the comparator 50 becomes unstable, so that an electronic circuit on a subsequent stage cannot be operated properly. In the circuit shown in FIG. 3A, the comparator 50 compares the compressed voltages va and vb with each other, and hence there arises a problem of the voltages being vulnerable to external noise. As shown in FIG. 3C, in the circuit shown in FIG. 3B, the signal Vx output from the comparator 60 changes in a range from 0 volt to the source voltage PVDD of the comparator 60. Accordingly, when the signal Vx output from the comparator 60 falls, a time is consumed before the output signal Vx falls from the source voltage PVDD to a threshold value of the level shift circuit 70. Hence, inversion of the level of the signal Vout output from the level shift circuit 70 is delayed, which raises a problem of an overall delay time for the comparator 60 and the level shift circuit 70 becoming longer.